SUCHIT SHAH

335 Huntington Ave, Apt #27, Boston, MA 02115 Ph: #857-222-9409

E-mail: shah.suc@neu.edu

 


EDUCATION

 


Northeastern University, Boston, MA                                                             GPA: 3.6/4.0               

Masters in Science (Electrical & Computer Engineering)                                                                    [January 2009]

Relevant Courses: VLSI Design, Analog Integrated Circuits, IC Fabrication, Solid State Devices, Electromagnetic Theory, Intro to MEMS and Financial Management for Engineers.

 

Gujarat University, Ahmedabad, India                                                                       GPA: 3.8/4.0                           

Bachelor of Engineering (Electrical Engineering)                                                                               [May 2006]

Relevant Courses: Linear Electronics, Digital Electronics, Integrated Electronics, Microprocessor Interfacing and Application, Advanced Microprocessors, Electrical Measurement & Measuring Instruments, Control Theory.

           

EXPERIENCE

 


Hardware Prototyping and Product Development

Independent Freelancer                                                                                 (January 2009 – Present)

·       Currently building a hardware prototype for an independent freelance project using Altera Cyclone II FPGA Development kit. The FPGA design entry is written in Verilog programming. The project involves development of a color sensor device on a PCB board.

 

Center for High Rate Nanomanufacturing, Northeastern University, Boston, MA.

Research Assistant                                                                                        (January 2008 – January 2009)

·       Research in Low Level Measurements and test system setups for characterization of MEMS, Carbon Nanotube (CNT) and Graphene based devices, transistors and logic switches. Developed test setups using rack & stack instruments approach for automated chip level testing.

·       Configured and automated Semiconductor Parametric Analyzers, Function Generators, SMUs, Lock in amplifiers, Oscilloscopes and DMMs. Built interface circuits & breakout boxes for logic analyzer, dynamic signal analyzers and distortion analyzers.

·       Designed experiments of test parameters for measuring properties and failure analysis of these devices. Involved in statistical analysis of test data and literature search for understanding device performance.

·        Investigated process parameters, modified fabrication conditions for optimum device operation and developed a novel design for high rate manufacturing of the nano-switch device.

 

Nantero, Woburn, MA.

Device Integration and R&D Department                                                       (May 2007 – December 2007)

·       Worked on design of layout and process flow, fabrication of devices, developing the test plan, reporting and assisting in product development.

·       Contributed in device manufacturing, test development, device characterization, failure analysis and yield improvement. Experience in wafer processing, CNT handling, micro-probing, AFM characterization, SEM imaging and Kalos Memory Tester.

·       Built the layout for the memory cube devices using GDS tool, automated the test result processing using PERL scripting, fabricated & tested CNT based switches & transistors, upgraded the Signatone DC Tester for device analysis and memory device testing.

 

Northeastern University, Boston, MA.

Graduate Assistant                                                                                         (January 2007 – May 2007)

·       Designed a tester for testing micro-switches using National Instruments 6281 DAQ board. Built the software for testing of MEMS Switches using LabVIEW 8.0 designed to measure switch resistance, calculate its threshold voltage and take Voff measurement to understand stiction.

 

Institute for Plasma Research, Gandhinagar, India.

Summer Internship, Department of Science & Technology                           (March 2006 – June 2006)

·       Developed an analog/digital optical circuit for 100 kV DC Isolation for RF and Microwave systems at Institute for Plasma Research, Department of Science and Technology, Government of India. The test circuit was simulated in MATLAB and interfaced with computer for real time data acquisition.

 

TECHNICAL SKILLS

 


Computer Skills:

o   Programming:  Visual Basic 6.0, 8086 Assembly Language, HTML, Flash, C, Verilog, HSPICE.

o   Scripting: PERL, UNIX shell scripting.

o   Tools: NI LabVIEW 8.2, MATLAB 6.0, CoolView GDS Tool, SynaptiCAD, Virtuoso Layout,

o   Simulation Tools: OrCAD PSpice, Simulink, Cadence, JMP, MegaStat, ModelSim, Quartus II, Active HDL.

 

Certifications:

·       LabVIEW: Certified National Instruments LabVIEW Associate Developer.

·       Six Sigma: Certified Yellow Belt in Six Sigma by Northeastern University’s Institute of Industrial Engineers.

·       Innovator: Awarded for Young Innovation Idea by National Innovation Foundation, Govt. of India, Ahmedabad.

 

Projects:

 

Technical Papers:

 

ACTIVITES

 


Leadership:

·       Selected as OASIS Leader by ISSI, Northeastern University.                                       [2006-2007]

Hobbies: Astronomy, Web Designing, Photography and Driving.

Editor: Author of blog on low-level measurement techniques & instrumentation circuits.

Sportsmanship: Selected as team leader for inter-company rowing competition representing Nantero company team.

References to be furnished upon Request

 

 

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